Technical Field
The present disclosure relates to vertically orientated memory devices, and methods of forming vertical memory devices. The methods and structures described herein integrate vertical field effect transistors with vertically orientated memory devices that include a floating gate.
Description of the Related Art
A Field Effect Transistor (FET) typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the channel. With ever decreasing device dimensions, forming the individual electrical components is becoming more difficult to manufacture. Vertical transistors are one means of scaling transistors to decreasing dimensions. Integration of memory devices with increasingly scaled transistors, such as vertical transistors, creates additional challenges. An approach is therefore needed that retains the positive aspects of traditional FET structures and memory devices, while overcoming the scaling issues created by forming smaller device components.